1. Field of the Invention
The present invention relates generally to a precise and programmable duty cycle generator, and more particularly pertains to a precise and programmable duty cycle generator which provides a programmable duty cycle clock from an input clock signal having any duty cycle.
Almost all ICs require a clock signal to accomplish their operations and be synchronous with other related components. The frequency of this clock determines the performance of the IC. As sub-micron technologies allow designs to operate at higher frequencies, design techniques must also provide for increasing their performance. An adjustable duty cycle clock circuit provides designers with flexibility in their designs, allowing them to meet high-performance and low-power goals. In addition to this flexibility, a programmable duty cycle adjuster provides robustness to the design. After fabrication, if the process was not modeled accurately, the duty cycle can be adjusted through the IC bus, fuses, or primary pins on the IC to operate the IC at the highest possible clock rate.
The present invention provides a circuit which provides a programmable duty cycle clock from an input clock signal having any duty cycle.
2. Discussion of the Prior Art
The idea of providing a circuit for duty cycle correction isn""t new. The prior art has circuits which correct an incoming signal""s duty cycle to a fixed value, typically 50xe2x80x9450.
The present invention differs from the prior art by allowing the output corrected signal to be programmable to any value duty cycle with precision.
U.S. Pat. No. 4,881,041 discloses a circuit to correct an incoming signal""s duty cycle to a 50/50 duty cycle and is limited to a 50/50 duty cycle correction with no provision for any other duty cycle, and the circuit is completely different from the present invention. U.S. Pat. No. 5,157,277 discloses a circuit to convert a sine wave input clock signal at a 50/50 duty cycle into a square wave signal with a variable duty cycle. The conversion circuit is limited to sine wave inputs, and is significantly different from the present invention which addresses square wave signals.
Accordingly, it is a primary object of the present invention to provide a precise and programmable duty cycle generator which can produce a user definable duty cycle clock signal with precision. This circuit is comprised of a number of generally known circuit elements such as a digital to analog converter (DAC), low pass filter (LPF), and operational transconductance amplifier (OTA), as well as a unique voltage controlled duty cycle generator (VCDCG). The circuit has the ability to produce a user programmable duty cycle clock signal with precision over a broad range of operational frequencies. The VCDCG circuit is unique and employs a number of stages, each of which has a current starved inverter which is immediately followed by a conventional inverter to allow duty cycle corrections to be either additive or subtractive. The current starved inverters are controlled by a single voltage, Vcont, and the series inverter isn""t voltage controlled at all. The single control voltage causes the current starved inverter""s delay to degrade/improve on one transition while improve/degrade on the other transition. For improved precision, a differential embodiment employs the same VCDCG.
A further object of the subject invention is the provision of an adjustable duty cycle clock circuit which provides designers with flexibility in their designs, allowing them to meet high-performance and low-power goals. In addition to this flexibility, a programmable duty cycle adjuster provides robustness to the design. After fabrication, if the process was not modeled accurately, the duty cycle can be adjusted through the IC bus, fuses, or primary pins on the IC to operate the IC at the highest possible clock rate.